1. Field of the Invention
The present invention relates to a NAND gate circuit used for a decoder circuit provided in a semiconductor memory device.
2. Description of the Related Art
FIG. 1(A) shows an ordinary conventional decoder circuit and in FIG. 1 V.sub.cc is a source voltage, for example 5 V, while V.sub.ss is a ground potential (0 V).
A transistor T.sub.1 used for a load means, for example, an N channel depletion type MOS transistor, and driving transistors T.sub.2 and T.sub.3, for example, N channel enhancement type MOS transistors used as a driving circuit, are provided.
In this NAND gate circuit, both an input a to the transistor T.sub.2 and an input b to the transistor T.sub.3 are binary signals and the transistors T.sub.2 and T.sub.3 are of the same type.
In the circuit, when fixing the voltage of the input a at 5 V, if the voltage of input b, for example, is increased from 0 V to 5 V or decreased from 5 V to 0 V, the output voltage V.sub.OUT which appears midway, changes from the voltage of nearly 5 V to nearly 0 V or from nearly 0 V to nearly 5 V.
Therefore, previously when the voltage exceeds 2 V, the level of the voltage should be discriminated as "H", and when lower than 2 V, it should be discriminated as "L", the output level of the NAND gate circuit fluctuates from "H" to "L" when the voltage of the input b is varied from 0 V to 5 V.
The same is true when the voltage of the input a is varied in the same way as above.
Note that, the input voltage at which the level of the output voltage of the NAND gate circuit changes from "H" to "L" or vice versa is called as the input threshold voltage of the NAND gate circuit.
In a NAND gate circuit, however, the input threshold voltage changes depending upon the formation of the input voltage applied to the input a and b.
Namely, the input threshold voltage of the NAND gate circuit differs as shown in FIG. 1(B), in three ways depending on whether the input voltage b was changed while the input voltage a was fixed at 5 V (only the input voltage b was changed) as shown by a curve (2) in FIG. 1(B), the input voltage a was changed while the input voltage b was fixed at 5 V (only the input voltage a was changed) as shown by a curve (1) in FIG. 1(B), or both the input voltages a and b were simultaneously changed (both the input voltages a and b are changed) as shown by a curve (3) in FIG. 1(B).
Note that, for example, the input threshold voltage of the NAND gate circuit obtained when only the input voltage b is changed and the input voltage a is fixed at 5 V is 1.5 V, the input threshold voltage obtained when the input voltage a is changed and the input voltage b is fixed at 5 V is 2.0 V, and the input threshold voltage obtained when both the input voltages a and b are simultaneously changed is 2.5 V.
The reasons why this happens in such a conventional NAND gate circuit are as follows;
First, when the input voltage b is changed while the input voltage a is fixed at 5 V, the source voltage of the transistor T.sub.3 is V.sub.ss, i.e., 0 V
When the input voltage a is changed while the input voltage b is fixed at 5 V, the drain voltage of the transistor T.sub.3 will be increased beyond 0 V due to the transistor T.sub.3 being ON, enabling current to flow therein.
The source voltage of the transistor T.sub.2 is increased beyond V.sub.ss, i.e., 0 V since the drain voltage of the transistor T.sub.3 corresponds to the a source voltage of the transistor T.sub.2.
Therefore, there is a "back gate effect" in which a threshold voltage V.sub.th of a transistor will be increased when the a source voltage thereof becomes higher than the substrate voltage.
Also, the gate-source voltage of the transistor T.sub.2 is reduced at that time. Therefore, the output of the NAND gate circuit cannot be reversed unless a relatively high voltage is applied to the input a of the transistor T.sub.2.
This means that, in this situation, the load of this circuit cannot be driven when the gate voltage of the transistor T.sub.2 is relatively high.
Second, the threshold voltage of the NAND gate circuit will be substantially increased since the total current driving performance of each transistor T.sub.2 and T.sub.3 is weakened compared with the performance obtained in the situation in which one of the input voltages a and b is fixed at 5 V.
As explained above, when the threshold voltage of the NAND gate circuit changes according to the combination of the input voltages, applied to the input terminals of the circuit, a problem arises in that the noise immunity, i.e., the immunity to noise for each signal input to a certain transistor will become different from the others and the total noise immunity will deteriorate accordingly.
This situation will be explained more specifically with respect to FIG. 1(B).
The transistors used in the NAND gate circuit is presented, as follows;
The transistors T.sub.2 and T.sub.3 have a threshold voltage V.sub.th of 0.6 V, a thickness of the gate oxide film of 350 .ANG., a gate width of 50 .mu.m, and a gate length of 2 .mu.m, while the transistor T.sub.1 has a threshold voltage V.sub.th of -3.5 V, a thickness of the a gate oxide film of 350.ANG., a gate width of 20 .mu.m, and a gate length of 5 .mu.m.
As apparent from FIG. 1(B), when the NAND gate circuit is operated at voltage V.sub.cc of 5 V, the input threshold voltage is 2.15 V, 1.95 V and 2.45 V obtained when the input voltage a alone is changed, the input voltage b alone is changed and both the input voltages a and b are simultaneously changed, respectively.
The curves (1), (2), and (3) show the an outputs of the NAND gate circuit according to the three formations of input voltages.
When the input threshold voltage of the NAND gate circuit changes with respect to the inputs to the circuit, the immunity to noise of the input voltages will become different, and thus the overall noise immunity of the circuit will detoriorate.
For example, as apparent from the curve (3), if the input voltages a and b are equally V.sub.cc =5 V, the NAND gate circuit outputs a voltage having a level of "H" instead of "L" when noise is added to any one of the input signals to reduce the input signal voltage level below 2.55 V.
While, if the input voltage a is set at V.sub.cc =5 V and the input voltage b is set at V.sub.ss =0 V, the NAND gate circuit outputs a voltage having a level of "L" instead of "H" when noise is added to the input signals to increase the input signal voltage level over 1.95 V.
This means that the noise immunity for the input voltage of the NAND gate circuit is 2.55 V for voltage descending from V.sub.cc and 1.95 V for voltage increasing from V.sub.ss.
Thus a poor noise immunity is obtained and a problem arises of deterioration of the overall noise immunity.
The more the driving transistors arranged serially in the driving circuit in the NAND gate circuit, the more remarkably the noise immunity is deteriorated.
There is thus a significant problem in a decoder circuit including an NAND gate circuit when there are more than five transistors serially arranged.
Namely, the conventional NAND gate circuit is weak against noises.
Note that, when a NAND gate circuit is deteriorated in noise immunity, it will frequently operate erroneously with respect to the signals input to the gates of the driving transistors of the driving circuit. Also, a NAND gate circuit is generally used for a main circuit of a decoder connected to a memory cell array in a memory device.
Therefore, when the NAND gate circuit erroneously operates due to noise added to the signals, input to the gates of the driving transistors, the erroneous information generated from the NAND gate circuit, i.e., decoder, significantly affects the memory cell array or the like in the memory device, causing erroneous information to be output from the memory device.
How the erroneous operation in a NAND gate circuit, i.e., decoder, affects a semiconductor memory device will be explained with reference to FIGS. 2 to 5.
Typical decoder consisting of NAND gate circuit has a circuit construction as shown in FIG. 2, as known from Japanese Unexamined Patent Publication (Kokai) No. 61-45496.
Referring first to FIG. 2, showing the circuit construction and operation of the prior art, in a decoder circuit consisting of NAND gate circuit, a source voltage V.sub.PPI can be internally switched to two different voltage levels such as a low voltage of about 5 V (referred to as V.sub.cc hereinafter) in a reading mode and a high voltage of about 12.5 V (referred to as V.sub.PP hereinafter) in a writing mode.
The decoder includes a decoder circuit and a CMOS inverter (IV).
In the decoder circuit, i.e., a NAND gate circuit, an N-channel depletion type MOS transistor T.sub.1 and N-channel enhancement type MOS transistors T.sub.2 to T.sub.5 are provided.
In the inverter, an N-channel enhancement type MOS transistor T.sub.7 and a P channel enhancement type MOS transistor T.sub.6 are provided.
As apparent from FIG. 2, the NAND gate circuit consists of the transistor T.sub.1 as a load means and the transistors T.sub.2 to T.sub.5 as a driving circuit.
The output N.sub.1 which drives the CMOS inverter (IV) consists of the transistors T.sub.6 and T.sub.7.
An output of the CMOS inverter (IV) connects to a word line (WL).
A memory cell transistor MC is provided at each cross point of the word line (WL) and bit lines BL.sub.0, BL.sub.1, BL.sub.2 . . . .
Input address signals a to d are applied to the gates of the driving transistors T.sub.2 to T.sub.5 , respectively.
In a stable condition, these input address signals selectively show either the V.sub.cc level (logic "1") or V.sub.ss level (logic "0", usually showing the ground level, i.e., 0 V).
When all the voltage levels of the input address signals a to d are V.sub.cc, the node N.sub.1 (output of 0 the decoder circuit) is reduced nearly to V.sub.ss, i.e., 0 V, regardless of whether the decoder source voltage V.sub.PPI is V.sub.cc or V.sub.pp.
Thus, the node N.sub.2, i.e., the output voltage of the inverter is increased to V.sub.PPI.
If one or more of the input address signals a to d is V.sub.ss, the output N.sub.1 of the decoder circuit (DEC) is increased to V.sub.PPI.
Thus, the output of the inverter N.sub.2 is reduced to V.sub.ss, i.e., 0 V.
Here, the input address signals a to d are given from, for example, the outputs of an address buffer circuit in which the address signals applied externally thereto are subjected to a waveform shaping operation inside the chip.
In a conventional semiconductor memory device, when the decoder once erroneously operates, erroneous information is transferred to a memory cell array and finally incorrect information is output from the memory device.
Generally speaking, as shown in FIG. 3, address signal inputs externally provided are applied to the input terminal of a buffer circuit with a waveform as shown in FIG. 3(a), are subjected to a waveform shaping operation, and are output to the input terminals of the decoder circuit with a waveform as shown in FIG. 3(b).
In this situation, suppose that when a noise Y is added to the address signal as shown in FIG. 3(a), the output signal of the address buffer inherently has the abnormal signal portion X and X' in response to the noise portion Y as shown in FIG. 3(b).
Then, when the output signal of the address buffer including such an abnormal signal portion X is input to the decoder circuit, the decoder will erroneously operate depending upon the level of the abnormal signal portion and the level of the threshold set for the decoder circuit.
If the level of the abnormal signal portion is higher or lower than the threshold level set for the decoder circuit, the decoder circuit will erroneously operate and output a erroneous signal information Z to the word line WL as shown in FIG. 3(c).
More specifically, when the decoder circuit is set to that, as shown in FIG. 4, outputs of the address buffer having the "H" level are applied to the gates a, b, and c of the transistors T.sub.2 to T.sub.4, the output thereof of the "L" level is applied to the gate d of the driving transistor T.sub.5 of the driving circuit of the decoder circuit, the input threshold voltage is set at 1.5 V.
Accordingly, in this situation, the output V.sub.OUT at the node N.sub.1 of the decoder circuit is at the "H" level and thus the output at the node N.sub.2 of the inverter is at the "L" level, as shown in FIG. 4,
Now, suppose that when an abnormal signal portion X having a level exceeding 1.5 V is instantly applied to the input terminal d, the level of the output V.sub.OUT of the decoder circuit is instantly switched to the "L" level instead of being the "H" level naturally, whereby the level of the output of the inverter is also instantly switched to the "H" level instead of being the "L" level naturally.
Therefore, in this situation, the word line WL connected to this decoder is a non-selected word line and thereby the signal level thereof inherently is "L", although the level of the word line will be increased from the level of 0 V to form an abnormal signal portion z as shown in FIG. 3(c) so as to mistakenly read or write information from or into a certain memory cell.
While, when the duration of such an abnormal signal portion is remarkably short, such a signal does not affect the circuits arranged downstream of the circuit concerned so much, although, when the duration is relatively long, the effect is considerable.
In a memory cell array used in a semiconductor memory device, a plurality of pairs of resistors and capacitors are serially arranged therein.
An equivalent circuit thereof can be drawn as shown in FIG. 5.
Therefore, a signal output from an inventor including an abnormal signal level will be delayed and the duration of the abnormal signal portion will be prolonged due to the existence of the plurality of time constants created by CR.
When such a prolonged signal portion p is output to the sense amplifier, the sense amplifier will necessarily read erroneous date p with a threshold level V.sub.L for a period t as shown in FIG. 9.
To avoid such erroneous operation of the decoder circuit and thus also the semiconductor memory device due to such deterioration of the overall noise immunity, it has been proposed to construct an address buffer circuit which will not respond to noise so sharply, but it is very difficult to completely prevent such problems by such a method.